Scaling integrated circuits is a continuous effort in the manufacturing of integrated circuits. Currently, small-scale integrated circuits, which may be manufactured using 15 nm technology, are being researched. For metal-oxide-semiconductor (MOS) devices, the scaling results in the potential for high performance.
When the MOS devices are manufactured using 15 nm technology, the effective oxide thickness (EOT) of gate dielectrics also need to be downscaled, for example, to about 0.5 nm. However, there exists a dilemma. In order to meet the 0.5 nm EOT target for 15 nm logic technology, a typical 0.5 nm to 1.0 nm SiO2 interfacial layer, which was commonly used in the state-of-the-art high-K/metal gate (HKMG) technology, has to be eliminated. However, when a commonly used Hf-based high-K dielectric is in direct contact with the underlying silicon channel, the carrier mobility in the channel region of the resulting MOS device was typically degraded to about 50% of a universal Si mobility (at a high electrical field, for example, about 1 MV/cm).
FIGS. 1 and 2 illustrate the intermediate stages in the manufacturing of a conventional MOS device. Referring to FIG. 1, silicon oxide interfacial layer 12 with a thickness of about 1 nm is on silicon substrate 10. High-K dielectric layer 14, which comprises HfO2, is deposited on interfacial layer 12 using atomic layer deposition (ALD). Next, a thin Hf layer 16 is formed on high-K dielectric layer 14 as an oxygen-scavenging agent to deprive oxygen from interfacial layer 12 (symbolized by arrows 15), resulting in the structure shown in FIG. 2. The thin Hf layer 16 is converted to HfO2 layer, and becomes part of high-K dielectric layer 14, also referred to as HfO2 layer 14. Since oxygen is removed from interfacial layer 12, interfacial layer 12 is either converted to silicon or intermix with HfO2 to form HfSiOx, which is equivalent to eliminating the silicon oxide interface layer 12. As a result, the EOT of the resulting gate dielectric is scaled down, for example, to 0.6 nm.
A drawback of the process shown in FIGS. 1 and 2 is that the carrier mobility in the channel region will be degraded to between about 90% and about 50% of the universal Si mobility. In addition, the breakdown voltage of the resulting gate dielectric is reduced. This is because the elimination of the silicon oxide interfacial layer will result in an increase in the coupling between the remote soft optical phonon modes of the high-K dielectric and the carriers in the channel region of the resulting MOS device, and hence, a lower carrier mobility. Therefore, there is a tradeoff between EOT scaling and mobility degradation.